公开(公告)号：US20160276336A1

公开(公告)日：2016-09-22

申请号：US14661202

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin LEE ,  Xiangxiang LU ,  Manjunatha PRABHU ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/7816 ,  H01L29/7835

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract translation: 提供了具有静电放电（ESD）保护和制造方法的高压半导体器件。 半导体器件包括在衬底上图案化的多个晶体管，该一个或多个公共栅极延伸穿过衬底的一部分，以及多个第一S / D触点和与公共栅极相关联的多个第二S / D触点 s）。 第二S / D触点设置在衬底内的多个载流子掺杂区域上。 一个或多个浮动节点设置在衬底上方，并且至少部分地设置在第二S / D触点之间，以有助于限定衬底内的多个载流子掺杂区域。 例如，载流子掺杂区域可以由具有公共载流子区域开口的掩模限定，浮动节点与公共载流子区域开口相交，并且有助于与公共开口一起限定多个分开的 载流子掺杂区域。

公开(公告)号：US20160064371A1

公开(公告)日：2016-03-03

申请号：US14471712

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jian-Hsing LEE ,  Jagar SINGH ,  Manjunatha PRABHU ,  Anil KUMAR ,  Mahadeva Iyer NATARAJAN ,  Min-hwa CHI

IPC: H01L27/02 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L27/0259

Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit.

Abstract translation: 保护非平面输出晶体管免受静电放电（ESD）事件包括提供非平面半导体结构，该结构包括具有n型或p型阱的半导体衬底。 提供的非平面结构还包括耦合到衬底的凸起的半导体结构，与阱相对的类型的非平面晶体管，每个晶体管位于凸起结构中的一个上， 每个包括源极，漏极和栅极的平面晶体管，非平面结构还包括在凸起结构上的寄生双极结晶体管（BJT（s）），每个BJT包括集电极和 位于凸起结构上的发射器和作为阱的基座，以及用于BJT的基座的阱接触。 保护非平面输出晶体管还包括将非平面晶体管的漏极和BJT的集电极电耦合到电路的输出，并且将非平面晶体管的源极，BJT的发射极和 接触到电路的地面。

公开(公告)号：US20160064372A1

公开(公告)日：2016-03-03

申请号：US14469155

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU ,  Anil KUMAR

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US20160054383A1

公开(公告)日：2016-02-25

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil KUMAR ,  Suresh UPPAL ,  Manjunatha PRABHU ,  William MCMAHON

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。

公开(公告)号：US20180342501A1

公开(公告)日：2018-11-29

申请号：US16055365

申请日：2018-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin LEE ,  Xiangxiang LU ,  Manjunatha PRABHU ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/7816 ,  H01L29/7835

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

公开(公告)号：US20180026028A1

公开(公告)日：2018-01-25

申请号：US15481202

申请日：2017-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin LEE ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L21/823431 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/785

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

公开(公告)号：US20160260701A1

公开(公告)日：2016-09-08

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU ,  Anil KUMAR

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract translation: 这里提出了配置为ESD保护装置的场效应晶体管（FET）。 在一个实施例中，FET可以被配置为以快速恢复操作模式操作。 FET可以包括半导体衬底，形成在衬底上的栅极和形成在与栅极间隔开的衬底上的伪栅极。

公开(公告)号：US20160035906A1

公开(公告)日：2016-02-04

申请号：US14450887

申请日：2014-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin LEE ,  Mahadeva Iyer NATARAJAN ,  Manjunatha PRABHU ,  Anil KUMAR ,  Ruchil Kumar JAIN

IPC: H01L29/861 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/66128

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract translation: 提供ESD器件用于保护电路免受静电放电，并且包括具有阳极和阴极的平面二极管。 阳极电耦合到电路的信号路径，并且阴极电耦合到电路的地。 ESD装置被配置为在电路的正常操作期间关闭并且响应于信号路径上的静电放电而导通。 器件中的两个耗尽区由隔离阱隔开。 响应于静电放电，耗尽区域调制（例如，加宽和合并），提供用于放电到电路接地的路径。