Invention Application
- Patent Title: COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
- Patent Title (中): 补充金属氧化物半导体器件及其形成方法
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Application No.: US14526552Application Date: 2014-10-29
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Publication No.: US20160093616A1Publication Date: 2016-03-31
- Inventor: Chien-Ming Lai , Chien-Chung Huang , Yu-Ting Tseng , Ya-Huei Tsai , Yu-Ping Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Priority: CN201410524514.7 20140930
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/49 ; H01L21/28 ; H01L21/8238
Abstract:
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
Public/Granted literature
- US09412743B2 Complementary metal oxide semiconductor device Public/Granted day:2016-08-09
Information query
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