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公开(公告)号：US20250048648A1
公开(公告)日：2025-02-06
申请号：US18916746
申请日：2024-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.
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公开(公告)号：US20240429093A1
公开(公告)日：2024-12-26
申请号：US18224576
申请日：2023-07-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Ting Lin , Kai-Kuang Ho , Chuan-Lan Lin , Yu-Ping Wang , Chu-Fu Lin , Yi-Feng Hsu , Yu-Jie Lin
IPC: H01L21/768 , H01L21/02 , H01L21/784 , H01L23/544
Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.
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公开(公告)号：US12156478B2
公开(公告)日：2024-11-26
申请号：US18110337
申请日：2023-02-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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公开(公告)号：US12146927B2
公开(公告)日：2024-11-19
申请号：US18376451
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US20240074328A1
公开(公告)日：2024-02-29
申请号：US18502109
申请日：2023-11-06
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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Patent Agency Ranking
公开(公告)号：US20230354716A1
公开(公告)日：2023-11-02
申请号：US18219713
申请日：2023-07-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
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公开(公告)号：US11800723B2
公开(公告)日：2023-10-24
申请号：US17019340
申请日：2020-09-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Hung-Yueh Chen , Rai-Min Huang , Jia-Rong Wu , Yu-Ping Wang
CPC classification number: H10B61/20 , G11C5/025 , G11C5/06 , G11C11/161 , H10N50/80
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.
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公开(公告)号：US20230247915A1
公开(公告)日：2023-08-03
申请号：US18132992
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.
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公开(公告)号：US11665973B2
公开(公告)日：2023-05-30
申请号：US17736069
申请日：2022-05-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
IPC: H10N50/01
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
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公开(公告)号：US20230154514A1
公开(公告)日：2023-05-18
申请号：US17548583
申请日：2021-12-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
CPC classification number: G11C11/161 , H01L43/12 , H01L43/10 , H01L43/08 , H01L43/02 , H01L27/222
Abstract: The invention provides a semiconductor structure, which comprises an MTJ (magnetic tunneling junction) stacked structure arranged on a substrate, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.
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