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    METHOD FOR REMOVING OXIDE
    2.
    发明申请
    METHOD FOR REMOVING OXIDE 有权
    去除氧化物的方法

    公开(公告)号：US20130316540A1

    公开(公告)日：2013-11-28

    申请号：US13966276

    申请日：2013-08-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Chu Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Keng-Jen Liu

    IPC: H01L21/3065

    CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/02063

    Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

    Abstract translation: 描述了一种去除氧化物的方法。 提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。 使用三氟化氮（NF3）和氨（NH3）作为反应气体对基板进行去除氧化处理，其中NF 3的体积流量大于NH 3的体积流量。

    Semiconductor device and manufacturing method of the same
    3.
    发明授权
    Semiconductor device and manufacturing method of the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US09076759B2

    公开(公告)日：2015-07-07

    申请号：US13737949

    申请日：2013-01-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Chien-Chung Huang ,  Kok Seen Lew

    IPC: H01L29/76 ,  H01L29/94 ,  H01L29/40 ,  H01L29/45

    CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.

    Abstract translation: 半导体器件包括半导体衬底，金属栅极结构，至少外延层，层间电介质，至少接触孔，至少金属硅化物层和含氟层。 半导体衬底至少具有栅极区域和至少与栅极区域相邻的源极/漏极区域。 栅极结构设置在栅极区域内的半导体衬底上。 外延层设置在源极/漏极区域内的半导体衬底上。 层间电介质覆盖半导体衬底，栅极结构和外延层。 接触孔穿透层间电介质到达外延层。 金属硅化物层形成在外延层中并且位于接触孔的底部。 含氟层设置在外延层中或外延层中并且在金属硅化物层的侧面附近。

    Method for manufacturing CMOS transistor
    4.
    发明授权
    Method for manufacturing CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US09502305B2

    公开(公告)日：2016-11-22

    申请号：US14060568

    申请日：2013-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

    IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

    Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

    Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

    METHOD FOR MANUFACTURING CMOS TRANSISTOR
    7.
    发明申请
    METHOD FOR MANUFACTURING CMOS TRANSISTOR 有权
    制造CMOS晶体管的方法

    公开(公告)号：US20140038374A1

    公开(公告)日：2014-02-06

    申请号：US14060568

    申请日：2013-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

    Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

    Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

    SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS
    10.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS 有权
    具有侧壁间隔的金属门的半导体结构

    公开(公告)号：US20150249142A1

    公开(公告)日：2015-09-03

    申请号：US14698828

    申请日：2015-04-28

    Applicant: United Microelectronics Corp.

    Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

    IPC: H01L29/66 ,  H01L21/263 ,  H01L29/40

    CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

    Abstract translation: 一种形成具有金属栅极的半导体结构的方法。 首先，提供半导体衬底。 随后，至少在半导体衬底上形成栅极结构。 之后，形成围绕栅结构的间隔结构。 然后，形成层间电介质。 之后，对层间电介质进行平面化处理。 然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。 暴露于开口的间隔结构的部分被去除以扩大开口。 之后，通过开口完全除去牺牲层。 最后，形成栅极导电层以填充开口。

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