Invention Application
- Patent Title: ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
- Patent Title (中): 电子封装及其制造方法
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Application No.: US14833586Application Date: 2015-08-24
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Publication No.: US20160148873A1Publication Date: 2016-05-26
- Inventor: Ching-Wen Chiang , Hsien-Wen Chen , Kuang-Hsin Chen , Chung-Chih Yen , Wei-Jen Chang
- Applicant: Siliconware Precision Industries Co., Ltd.
- Priority: KRTW103140748 20141125
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/768

Abstract:
A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing an electronic element in the cavity; forming a dielectric layer on the substrate and the electronic element; forming a circuit layer on the dielectric layer and forming a first conductive portion in the first via hole; forming on the substrate a second via hole communicating with the first via hole, the first and second via holes constituting a through hole; and forming a second conductive portion in the second via hole, the first and second conductive portions constituting a conductor. Since the through hole is formed through a two-step process, the invention can reduce the depth of the via holes and therefore perform laser drilling or etching processes with reduced energy, thereby avoiding damage of the conductive portions and improving the product reliability.
Information query
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