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    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
    1.
    发明申请
    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    电子封装及其制造方法

    公开(公告)号：US20160148873A1

    公开(公告)日：2016-05-26

    申请号：US14833586

    申请日：2015-08-24

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Hsien-Wen Chen ,  Kuang-Hsin Chen ,  Chung-Chih Yen ,  Wei-Jen Chang

    IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768

    CPC classification number: H01L23/5384 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/37001

    Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing an electronic element in the cavity; forming a dielectric layer on the substrate and the electronic element; forming a circuit layer on the dielectric layer and forming a first conductive portion in the first via hole; forming on the substrate a second via hole communicating with the first via hole, the first and second via holes constituting a through hole; and forming a second conductive portion in the second via hole, the first and second conductive portions constituting a conductor. Since the through hole is formed through a two-step process, the invention can reduce the depth of the via holes and therefore perform laser drilling or etching processes with reduced energy, thereby avoiding damage of the conductive portions and improving the product reliability.

    Abstract translation: 提供一种制造电子封装的方法，其包括以下步骤：提供具有空腔和第一通孔的基板; 将电子元件放置在空腔中; 在所述基板和所述电子元件上形成介电层; 在所述电介质层上形成电路层，并在所述第一通孔中形成第一导电部分; 在所述基板上形成与所述第一通孔连通的第二通孔，所述第一通孔和第二通孔构成通孔; 以及在所述第二通孔中形成第二导电部分，所述第一和第二导电部分构成导体。 由于通孔是通过两步法形成的，所以本发明可以减小通孔的深度，从而能够以较低的能量进行激光打孔或蚀刻处理，从而避免导电部的损坏，提高产品的可靠性。

    INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    用于其包装和制造方法的互连结构

    公开(公告)号：US20140217605A1

    公开(公告)日：2014-08-07

    申请号：US13894687

    申请日：2013-05-15

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chun-Hung Lin ,  Chun-Hung Lu ,  Guang-Hwa Ma ,  Hsiao-Chun Huang ,  Kuang-Hsin Chen

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53295 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/49894 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

    Abstract translation: 公开了一种用于封装的互连结构。 互连结构包括在其表面上形成有导电部分的基板主体; 形成在所述基板主体的表面上并且具有用于使所述导电部暴露的通孔的第一光敏介电层; 在通孔中形成的导电通孔; 形成在所述第一光敏介电层上并具有用于使所述导电通孔和所述第一光敏介电层的一部分暴露的开口的第二光敏介电层; 以及形成在第二感光介电层的开口中的导电迹线层，以便通过导电通孔电连接到导电部分，从而简化制造工艺并降低制造成本和时间。

    Method of fabricating electronic package
    6.
    发明授权
    Method of fabricating electronic package 有权

    公开(公告)号：US10199320B2

    公开(公告)日：2019-02-05

    申请号：US15784782

    申请日：2017-10-16

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

    IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/13

    Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.

    Electronic package and fabrication method thereof and substrate structure
    9.
    发明授权
    Electronic package and fabrication method thereof and substrate structure 有权

    公开(公告)号：US10049973B2

    公开(公告)日：2018-08-14

    申请号：US14984256

    申请日：2015-12-30

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

    Abstract: A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.

    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE STRUCTURE
    10.
    发明申请
    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE STRUCTURE 审中-公开
    电子封装及其制造方法及基板结构

    公开(公告)号：US20160276256A1

    公开(公告)日：2016-09-22

    申请号：US14984256

    申请日：2015-12-30

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81005 ,  H01L2924/15311

    Abstract: A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.

    Abstract translation: 提供了一种基板结构，其包括：具有相对的第一和第二表面的基板主体; 形成在所述基板主体的所述第一表面上并电连接到所述基板主体的多个导电柱; 以及形成在所述基板主体的第一表面上用于封装所述导电柱的电介质层，其中所述导电柱的一个端面从所述电介质层露出。 因此，本发明用传统的硅衬底替代传统的硅衬底，以消除制造常规TSV（通硅通孔）的需要，从而大大降低制造成本。 本发明还提供一种具有基板结构的电子封装及其制造方法。

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