Invention Application
US20160181439A1 TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRICATION PROCESS
审中-公开
包含在剪切应变和制造过程中放置的通道的晶体管
- Patent Title: TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRICATION PROCESS
- Patent Title (中): 包含在剪切应变和制造过程中放置的通道的晶体管
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Application No.: US14978778Application Date: 2015-12-22
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Publication No.: US20160181439A1Publication Date: 2016-06-23
- Inventor: Emmanuel AUGENDRE , Maxime ARGOUD , Sylvain MAITREJEAN , Pierre MORIN , Raluca TIRON
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Priority: FR1463176 20141223
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/12 ; H01L29/10 ; H01L29/78 ; H01L29/66
Abstract:
A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
Public/Granted literature
- US10978594B2 Transistor comprising a channel placed under shear strain and fabrication process Public/Granted day:2021-04-13
Information query
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