公开(公告)号：US20240411057A1

公开(公告)日：2024-12-12

申请号：US18632562

申请日：2024-04-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Raphaël FEOUGIER ,  Nicolas POSSEME ,  Raluca TIRON ,  Maxime ARGOUD

IPC: G02B3/00 ,  B81C1/00

Abstract: A method for manufacturing a three-dimensional structure comprising supplying a stack comprising, stacked in a vertical direction, a support substrate, a sacrificial layer, a layer of interest having a sidewall and a tensor layer having a sidewall, the tensor layer having a residual stress. The method also comprises removing a removal portion of the sacrificial layer, while retaining a remaining portion of the sacrificial layer underlying the layer of interest. The removal portion is located in line with a lateral portion of the layer of interest extending from the entire sidewall of the layer of interest. The residual stress of the tensor layer is configured to cause bending of the layer of interest during the step of removing the removal portion.

公开(公告)号：US20160181439A1

公开(公告)日：2016-06-23

申请号：US14978778

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Emmanuel AUGENDRE ,  Maxime ARGOUD ,  Sylvain MAITREJEAN ,  Pierre MORIN ,  Raluca TIRON

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/78654

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Abstract translation: 包括有源区的场效应晶体管包括源极，沟道，漏极和控制栅极，其与沟道水平定位，允许电流沿x轴流过源极和漏极之间的沟道， 所述通道包括：与所述源分离的第一边缘; 和与排水管分离的第二边缘; 所述通道被压缩或拉伸应变，其中所述通道包括沿通道的至少第一和/或第二边缘的局部穿孔或一组局部穿孔，以便也在通道中产生至少一个剪切应变。 提供了制造晶体管的工艺。

公开(公告)号：US20130156989A1

公开(公告)日：2013-06-20

申请号：US13718037

申请日：2012-12-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Hubert MORICEAU ,  Maxime ARGOUD ,  Frank FOURNEL ,  Frederic MAZEN ,  Christophe MORALES

IPC: B32B38/10 ,  B32B3/02 ,  B32B7/02

CPC classification number: B32B38/10 ,  B32B3/02 ,  B32B7/02 ,  H01L21/76254 ,  Y10T428/21 ,  Y10T428/24942 ,  Y10T428/24967

Abstract: A method for manufacturing a flexible structure including implanting ionic species in first and second source substrates so as to form first and second embrittlement regions respectively, delimiting first and second thin films, providing a flexible substrate, the stiffness R of which is less than or equal to 107 GPa·μm3, securing the first and second thin films to the first and second faces of the flexible substrate respectively so as to form a stack including the flexible structure delimited by the first and second embrittlement regions, the flexible structure having a stiffening effect suitable for allowing transfers of the first and second thin films, and applying a thermal budget so as to transfer the first and second thin films onto the flexible substrate.

Abstract translation: 一种用于制造柔性结构的方法，包括在第一和第二源基底中注入离子物质，分别形成第一和第二脆化区域，限定第一和第二薄膜，提供柔性基底，其刚度R小于或等于 至107GPa·mum3，分别将第一和第二薄膜固定到柔性基板的第一和第二表面，以便形成包括由第一和第二脆化区限定的柔性结构的堆叠，柔性结构具有加强效果 适于允许第一和第二薄膜的转印，以及施加热预算以将第一和第二薄膜转移到柔性基板上。

公开(公告)号：US20220149245A1

公开(公告)日：2022-05-12

申请号：US17435102

申请日：2020-03-02

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Aurélien SUHM ,  Maxime ARGOUD

IPC: H01L33/44 ,  G03F7/16 ,  G03F7/11

Abstract: A method for coating chips resting, by a rear face opposite to a front face, on a main face of a support substrate, and separated from each other by an inter-chip space, includes a step of forming a photosensitive coating film covering the front faces and the inter-chip spaces. The method further includes a first photolithographic sequence which comprises an insolation sub-step, and a dissolution sub-step. The sequence leads to a partial removal of the photosensitive coating film so as to maintain the film exclusively at the inter-chip spaces and, advantageously recessed relative to the front faces.

公开(公告)号：US20210104634A1

公开(公告)日：2021-04-08

申请号：US17123231

申请日：2020-12-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Emmanuel AUGENDRE ,  Maxime ARGOUD ,  Sylvain MAITREJEAN ,  Pierre MORIN ,  Raluca TIRON

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

公开(公告)号：US20190267233A1

公开(公告)日：2019-08-29

申请号：US16343774

申请日：2017-10-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Guillaume CLAVEAU ,  Maxime ARGOUD ,  Nicolas POSSEME ,  Raluca TIRON

IPC: H01L21/027 ,  G03F7/00 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

Abstract: A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer.