公开(公告)号：US20170345915A1

公开(公告)日：2017-11-30

申请号：US15603738

申请日：2017-05-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  IBM CORPORATION

Inventor： Remi COQUAND ,  Emmanuel AUGENDRE ,  Nicolas LOUBET ,  Shay REBOH

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.

公开(公告)号：US20160254362A1

公开(公告)日：2016-09-01

申请号：US15049468

申请日：2016-02-22

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Sylvain MAITREJEAN ,  Emmanuel AUGENDRE ,  Jean-Charles BARBE ,  Benoit MATHIEU ,  Yves MORAND

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/78696

Abstract: A Method for modifying the strain state of a semiconducting structure, comprising steps to: a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on the first semiconducting material and elements based on the second semiconducting material, then b) remove portions of the second semiconducting material from the first structure so as to form empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material, e) perform appropriate thermal annealing so as to make the dielectric material creep or relax, and cause a change in the strain state of elements based on the first semiconducting material in the structure.

Abstract translation: 一种用于修改半导体结构的应变状态的方法，包括以下步骤：a）在衬底上提供至少一个第一半导体结构，所述第一半导体结构由包括基于所述第一半导体材料的元件交替的半导体堆叠形成，并且基于 第二半导体材料，然后b）从第一结构去除部分第二半导体材料以形成空的空间，c）用介电材料填充空的空间，d）在第一结构上形成应变区，基于 第一应变材料，e）进行适当的热退火，以使电介质材料蠕变或松弛，并引起基于结构中的第一半导体材料的元件的应变状态的变化。

公开(公告)号：US20200321452A1

公开(公告)日：2020-10-08

申请号：US16904138

申请日：2020-06-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay REBOH ,  Emmanuel AUGENDRE ,  Remi COQUAND ,  Nicolas LOUBET

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis.

公开(公告)号：US20180204931A1

公开(公告)日：2018-07-19

申请号：US15842245

申请日：2017-12-14

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Shay REBOH ,  Emmanuel AUGENDRE ,  Remi COQUAND

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.

公开(公告)号：US20250022711A1

公开(公告)日：2025-01-16

申请号：US18768121

申请日：2024-07-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Emmanuel AUGENDRE ,  Pablo ACOSTA ALBA ,  Shay REBOH ,  Olivier ROZEAU

IPC: H01L21/225

Abstract: A method for producing a uniaxial stress state in a semiconductive layer, may include: providing a stack including a support, the semiconductive layer, and an inserted fuse layer; forming a stress donor layer on the semiconductive layer; partially altering the stress donor layer, modifying a first stress state of the layer to obtain a second stress state in one single direction; and melting the fuse layer, such that the stress donor layer transfers, by relaxation, the second stress state into the semiconductive layer.

公开(公告)号：US20180301341A1

公开(公告)日：2018-10-18

申请号：US15938321

申请日：2018-03-28

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Remi COQUAND ,  Emmanuel AUGENDRE ,  Shay REBOH

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78696

Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.

公开(公告)号：US20170330958A1

公开(公告)日：2017-11-16

申请号：US15583304

申请日：2017-05-01

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Remi COQUAND ,  Emmanuel AUGENDRE ,  Shay REBOH

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/66666 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7371 ,  H01L29/7827 ,  H01L29/78642

Abstract: A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.

公开(公告)号：US20170076944A1

公开(公告)日：2017-03-16

申请号：US15260767

申请日：2016-09-09

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel AUGENDRE ,  Aomar Halimaoui ,  Sylvain Maitrejean ,  Shay Reboh

IPC: H01L21/02 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/165 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L21/02694 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78687

Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s) d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

公开(公告)号：US20210104634A1

公开(公告)日：2021-04-08

申请号：US17123231

申请日：2020-12-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Emmanuel AUGENDRE ,  Maxime ARGOUD ,  Sylvain MAITREJEAN ,  Pierre MORIN ,  Raluca TIRON

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

公开(公告)号：US20170263495A1

公开(公告)日：2017-09-14

申请号：US15457447

申请日：2017-03-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Emmanuel AUGENDRE ,  Nicolas LOUBET ,  Sylvain MAITREJEAN ,  Pierre MORIN

IPC: H01L21/762 ,  H01L29/16 ,  H01L29/78

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.