Invention Application
- Patent Title: METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION
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Application No.: US15170273Application Date: 2016-06-01
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Publication No.: US20160276463A1Publication Date: 2016-09-22
- Inventor: DECHAO GUO , SHOGO MOCHIZUKI , ANDREAS SCHOLZE , CHUN-CHEN YEH
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , RENESAS ELECTRONICS CORPORATION
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/225 ; H01L21/324 ; H01L29/08
Abstract:
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
Public/Granted literature
- US09786661B2 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction Public/Granted day:2017-10-10
Information query
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