A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.