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公开(公告)号：US20160293241A1
公开(公告)日：2016-10-06
申请号：US14676292
申请日：2015-04-01
发明人： JOHN K. DEBROSSE , BLAKE G. FITCH , MICHELE M. FRANCESCHINI , TODD E. TAKKEN , DANIEL C. WORLEDGE
IPC分类号： G11C11/16
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
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公开(公告)号：US20170075592A1
公开(公告)日：2017-03-16
申请号：US15343861
申请日：2016-11-04
发明人： JOHN K. DEBROSSE , BLAKE G. FITCH , MICHELE M. FRANCESCHINI , TODD E. TAKKEN , DANIEL C. WORLEDGE
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.
摘要翻译： 一种用于存储器管理的方法包括使用优化对存储器件的写入速度的写数据通道的存储器设备中的存储器缓冲器的流比特流。 这些位使用双向总线以第一速度写入存储器件中的非易失性存储器单元。 通过读通道从存储器件读取位，以使用双向总线提供比第一速度慢的第二速度的读取。
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公开(公告)号：US20170017396A1
公开(公告)日：2017-01-19
申请号：US15272933
申请日：2016-09-22
发明人： JOHN K. DEBROSSE , BLAKE G. FITCH , MICHELE M. FRANCESCHINI , TODD E. TAKKEN , DANIEL C. WORLEDGE
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
摘要翻译： 存储器包括多个非易失性存储器件，每个具有多个非易失性存储器单元。 写控制器被配置为使用写数据信道将比特流传送到存储器设备，该写数据信道优化写入存储器件的速度以提供第一速度的写入。 读取控制器被配置为使用读取通道以比第一速度慢的第二速度从存储器件读取位。 写控制器和自参考读取控制器共享以访问多个非易失性存储器设备的双向总线。
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公开(公告)号：US20160291870A1
公开(公告)日：2016-10-06
申请号：US14747976
申请日：2015-06-23
发明人： JOHN K. DEBROSSE , BLAKE G. FITCH , MICHELE M. FRANCESCHINI , TODD E. TAKKEN , DANIEL C. WORLEDGE
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
摘要翻译： 存储器包括非易失性存储器件，每个存储器件具有多个非易失性存储器单元。 写控制器使用具有写总线驱动器，接收器和写总线拓扑的写数据通道以N组的方式将比特流分组到存储器件，其利用高速信令优化对存储器件的写入速度。 连续的比特组被写入相应的存储器件中的连续的存储器单元。 自参考读取控制器使用具有读驱动器，接收器和读总线拓扑的读通道从存储器件读取位，其中不包括高速或低延迟数据传输的设计要求。
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