Invention Application
US20160372561A1 MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
审中-公开
在FDSOI基板中形成垂直选择栅的存储单元
- Patent Title: MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
- Patent Title (中): 在FDSOI基板中形成垂直选择栅的存储单元
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Application No.: US15252090Application Date: 2016-08-30
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Publication No.: US20160372561A1Publication Date: 2016-12-22
- Inventor: Arnaud Regnier , Jean-Michel Mirabel , Stephan Niel , Francesco La Rosa
- Applicant: STMicroelectronics (Rousset) SAS
- Priority: FR1462642 20141217
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L27/115 ; H01L29/788 ; H01L29/66

Abstract:
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
Public/Granted literature
- US09691866B2 Memory cell having a vertical selection gate formed in an FDSOI substrate Public/Granted day:2017-06-27
Information query
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