-
公开(公告)号：US11004785B2
公开(公告)日：2021-05-11
申请号：US16546569
申请日：2019-08-21
发明人： Abderrezak Marzaki , Arnaud Regnier , Stephan Niel
IPC分类号： H01L23/522 , H01L49/02 , H01L27/11524
摘要： First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
-
公开(公告)号：US10796763B2
公开(公告)日：2020-10-06
申请号：US16256525
申请日：2019-01-24
发明人： Francesco La Rosa , Marc Mantelli , Stephan Niel , Arnaud Regnier
摘要： A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
-
公开(公告)号：US10770357B2
公开(公告)日：2020-09-08
申请号：US16429836
申请日：2019-06-03
IPC分类号： H01L21/8234 , H01L21/762 , H01L21/74 , H01L27/08 , H01L49/02 , H01C7/12 , H01L21/765 , H01L29/8605 , H01L29/06 , H01L23/522
摘要： An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
-
公开(公告)号：US10403730B2
公开(公告)日：2019-09-03
申请号：US15914846
申请日：2018-03-07
IPC分类号： H01L29/788 , H01L29/423 , H01L21/28 , H01L29/66 , H01L27/11521 , G11C16/14 , H01L21/3205 , H01L21/3213 , H01L27/11524 , H01L29/78 , G11C16/04 , H01L21/306
摘要： The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
-
公开(公告)号：US20190067309A1
公开(公告)日：2019-02-28
申请号：US16175030
申请日：2018-10-30
发明人： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC分类号： H01L27/11531 , H01L29/861 , G11C16/04 , H01L29/739 , H01L29/66 , H01L29/788 , H01L21/265 , H01L21/266 , H01L21/28 , H01L29/16 , H01L27/11526 , H01L27/11521 , H01L27/08 , H01L27/11536 , H01L27/12 , H01L27/06 , H01L29/36
摘要： An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.
-
公开(公告)号：US20180269115A1
公开(公告)日：2018-09-20
申请号：US15897003
申请日：2018-02-14
申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
发明人： Franck Julien , Stephan Niel , Emmanuel Richard , Olivier Weber
CPC分类号： H01L21/84 , H01L21/28008 , H01L21/82345 , H01L21/823462 , H01L27/0922 , H01L27/1207 , H01L29/51
摘要： A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.
-
公开(公告)号：US09941369B2
公开(公告)日：2018-04-10
申请号：US15195784
申请日：2016-06-28
IPC分类号： H01L29/788 , H01L29/423 , H01L21/28 , H01L29/66 , H01L27/11521 , G11C16/14 , H01L21/3205 , H01L21/3213 , H01L27/11524 , H01L29/78 , G11C16/04 , H01L21/306
CPC分类号： H01L29/42328 , G11C16/0425 , G11C16/14 , H01L21/28273 , H01L21/30604 , H01L21/32051 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L29/42336 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/788 , H01L29/7881 , H01L29/7883 , H01L29/7885
摘要： The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
-
公开(公告)号：US20170345836A1
公开(公告)日：2017-11-30
申请号：US15364603
申请日：2016-11-30
发明人： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC分类号： H01L27/11531 , H01L29/788 , H01L29/66 , H01L27/11526 , H01L27/11521 , H01L21/28 , H01L21/266 , H01L21/265 , H01L29/861 , G11C16/04
CPC分类号： H01L27/11531 , G11C16/045 , H01L21/26513 , H01L21/266 , H01L21/28273 , H01L27/0629 , H01L27/0814 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/1203 , H01L29/16 , H01L29/36 , H01L29/66136 , H01L29/66356 , H01L29/66825 , H01L29/7391 , H01L29/7394 , H01L29/788 , H01L29/861
摘要： A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.
-
公开(公告)号：US20170278577A1
公开(公告)日：2017-09-28
申请号：US15365433
申请日：2016-11-30
发明人： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC分类号： G11C16/34 , G11C16/26 , H01L29/788 , G11C16/08 , H01L27/115 , H01L29/792 , G11C16/04 , G11C16/10
CPC分类号： H01L29/7889 , G11C16/0433 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L28/00 , H01L29/788 , H01L29/792
摘要： The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.
-
公开(公告)号：US20170011804A1
公开(公告)日：2017-01-12
申请号：US15276462
申请日：2016-09-26
发明人： Francesco La Rosa , Stephan Niel , Arnaud Regnier
CPC分类号： G11C16/26 , G11C16/0408 , G11C16/0433 , G11C16/0441 , G11C16/08 , G11C16/14 , H01L21/0276 , H01L21/28273 , H01L27/0207 , H01L27/11521 , H01L27/11524
摘要： The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
摘要翻译： 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.054 秒)
