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    Non-volatile memory data bus
    3.
    发明授权
    Non-volatile memory data bus 有权

    公开(公告)号：US11056180B2

    公开(公告)日：2021-07-06

    申请号：US16853036

    申请日：2020-04-20

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4099 ,  G11C5/02

    Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.

    Structure and Method of Forming a Semiconductor Device
    4.
    发明申请
    Structure and Method of Forming a Semiconductor Device 有权

    公开(公告)号：US20210066510A1

    公开(公告)日：2021-03-04

    申请号：US16560810

    申请日：2019-09-04

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L29/861 ,  H01L27/07 ,  H01L29/66 ,  H01L29/788

    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

    DEVICE OF PHYSICALLY UNCLONABLE FUNCTION WITH FLOATING GATE TRANSISTORS, AND MANUFACTURING METHOD
    5.
    发明申请
    DEVICE OF PHYSICALLY UNCLONABLE FUNCTION WITH FLOATING GATE TRANSISTORS, AND MANUFACTURING METHOD 审中-公开

    公开(公告)号：US20200274723A1

    公开(公告)日：2020-08-27

    申请号：US16784495

    申请日：2020-02-07

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: H04L9/32 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30 ,  H04L9/06

    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.

    Reading circuit with a shifting stage and corresponding reading method
    8.
    发明授权
    Reading circuit with a shifting stage and corresponding reading method 有权

    公开(公告)号：US10127966B2

    公开(公告)日：2018-11-13

    申请号：US15389751

    申请日：2016-12-23

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

    IPC: G11C11/24 ,  G04F10/10

    Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

    Dynamic sense amplifier with offset compensation
    10.
    发明授权
    Dynamic sense amplifier with offset compensation 有权

    公开(公告)号：US09698765B1

    公开(公告)日：2017-07-04

    申请号：US15049944

    申请日：2016-02-22

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

    Inventor： Francesco La Rosa ,  Antonino Conte

    IPC: G11C11/22 ,  G11C11/00 ,  H03K5/003 ,  H03K17/687 ,  G11C7/06 ,  G11C7/12

    CPC classification number: H03K5/003 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12

    Abstract: A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.

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