Invention Application
US20170005621A1 SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING
审中-公开
具有隔离墙的半导体封装件可减少电磁耦合
- Patent Title: SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING
- Patent Title (中): 具有隔离墙的半导体封装件可减少电磁耦合
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Application No.: US15267455Application Date: 2016-09-16
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Publication No.: US20170005621A1Publication Date: 2017-01-05
- Inventor: Margaret A. Szymanowski , Sarmad K. Musa , Fernando A. Santos , Mahesh K. Shah
- Applicant: Freescale Semiconductor, Inc.
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H01L23/495 ; H01L23/552 ; H03F3/195 ; H01L25/065 ; H01L25/00 ; H01L21/48 ; H03F3/213 ; H01L23/00 ; H03F3/21

Abstract:
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
Public/Granted literature
- US10110170B2 Semiconductor package having an isolation wall to reduce electromagnetic coupling Public/Granted day:2018-10-23
Information query
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