公开(公告)号：US09450547B2

公开(公告)日：2016-09-20

申请号：US14104870

申请日：2013-12-12

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/552 ,  H01L21/56 ,  H03F3/213 ,  H03F1/02 ,  H01L23/492

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件的系统和方法。 半导体器件具有基板，第一电路和第二电路在其上彼此靠近地形成。 导电材料的隔离壁位于第一电路和第二电路之间，隔离壁被配置为在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 介绍了几种类型的隔离墙。

公开(公告)号：US09800208B2

公开(公告)日：2017-10-24

申请号：US15044701

申请日：2016-02-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Mahesh K. Shah ,  Jerry L. White ,  Li Li ,  Hussain H. Ladhani ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan ,  Fernando A. Santos

IPC: H03F1/00 ,  H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H03F1/56 ,  H03F3/21 ,  H03F1/30 ,  H03H1/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/66 ,  H03F3/193 ,  H05K7/00 ,  H01L23/64 ,  H03H7/38

CPC classification number: H03F1/0288 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2223/6666 ,  H01L2224/49175 ,  H01L2924/0002 ,  H03F1/0283 ,  H03F1/30 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/267 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2203/21103 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03H1/00 ,  H03H7/38 ,  H03H2001/0021 ,  H05K7/005 ,  H01L2924/00

Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

公开(公告)号：US20170005621A1

公开(公告)日：2017-01-05

申请号：US15267455

申请日：2016-09-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H03F1/02 ,  H01L23/495 ,  H01L23/552 ,  H03F3/195 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H03F3/213 ,  H01L23/00 ,  H03F3/21

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件的系统和方法。 半导体器件具有基板，第一电路和第二电路在其上彼此靠近地形成。 导电材料的隔离壁位于第一电路和第二电路之间，隔离壁被配置为在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 介绍了几种类型的隔离墙。

公开(公告)号：US09484222B2

公开(公告)日：2016-11-01

申请号：US14184266

申请日：2014-02-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Hussain H. Ladhani ,  Lu Li ,  Mahesh K. Shah ,  Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H01L23/02 ,  H01L27/08 ,  H01L21/48 ,  H03F3/193 ,  H03F3/21 ,  H01L25/00 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195

CPC classification number: H01L21/4853 ,  H01L23/66 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F2200/423 ,  H03F2200/451 ,  H01L2924/00014

Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.

Abstract translation: 公开了一种半导体器件，相关封装及其制造方法。 在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。 半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。 第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。

公开(公告)号：US10110170B2

公开(公告)日：2018-10-23

申请号：US15267455

申请日：2016-09-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H03F1/02 ,  H01L23/495 ,  H01L23/552 ,  H03F3/213 ,  H01L23/31 ,  H01L23/492 ,  H01L23/66 ,  H03F3/195 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H03F3/21

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

公开(公告)号：US09300254B2

公开(公告)日：2016-03-29

申请号：US14316484

申请日：2014-06-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Mahesh K. Shah ,  Jerry L. White ,  Li Li ,  Hussain H. Ladhani ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan ,  Fernando A. Santos

IPC: H03F3/213 ,  H03F1/30 ,  H03H1/00 ,  H03F3/195

CPC classification number: H03F1/0288 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2223/6666 ,  H01L2224/49175 ,  H01L2924/0002 ,  H03F1/0283 ,  H03F1/30 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/267 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2203/21103 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03H1/00 ,  H03H7/38 ,  H03H2001/0021 ,  H05K7/005 ,  H01L2924/00

Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

Abstract translation: 射频（RF）器件的一个实施例包括至少一个晶体管，封装和表面贴装电容器。 该封装包含至少一个晶体管，并且包括至少一个端接。 表面安装电容器以至少一个晶体管和该器件的电源端之间的分流配置耦合，以将至少一个晶体管与电源分离。

公开(公告)号：US20150235933A1

公开(公告)日：2015-08-20

申请号：US14184266

申请日：2014-02-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Hussain H. Ladhani ,  Lu Li ,  Mahesh K. Shah ,  Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L21/4853 ,  H01L23/66 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F2200/423 ,  H03F2200/451 ,  H01L2924/00014

Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.

Abstract translation: 公开了一种半导体器件，相关封装及其制造方法。 在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。 半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。 第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。