公开(公告)号：US20170005621A1

公开(公告)日：2017-01-05

申请号：US15267455

申请日：2016-09-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H03F1/02 ,  H01L23/495 ,  H01L23/552 ,  H03F3/195 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H03F3/213 ,  H01L23/00 ,  H03F3/21

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件的系统和方法。 半导体器件具有基板，第一电路和第二电路在其上彼此靠近地形成。 导电材料的隔离壁位于第一电路和第二电路之间，隔离壁被配置为在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 介绍了几种类型的隔离墙。

公开(公告)号：US09831835B2

公开(公告)日：2017-11-28

申请号：US15055330

申请日：2016-02-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Sarmad K. Musa ,  Ramanujam Srinidhi Embar

IPC: H03F3/68 ,  H03F1/02 ,  H03F3/21 ,  H03F3/19 ,  H01P5/12

CPC classification number: H03F1/0288 ,  H01P5/12 ,  H03F1/07 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/451 ,  H03F2203/21142

Abstract: A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal carried by the first signal conduction path. A delay element is configured to impose a phase delay on the output signal of the first coupler to generate a delayed output signal. The device includes a second coupler coupled to the second signal conduction path. The second coupler is connected to the delay element and configured to inject the delayed output signal into the second signal conduction path.

公开(公告)号：US10110170B2

公开(公告)日：2018-10-23

申请号：US15267455

申请日：2016-09-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H03F1/02 ,  H01L23/495 ,  H01L23/552 ,  H03F3/213 ,  H01L23/31 ,  H01L23/492 ,  H01L23/66 ,  H03F3/195 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H03F3/21

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

公开(公告)号：US20170250656A1

公开(公告)日：2017-08-31

申请号：US15055330

申请日：2016-02-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Sarmad K. Musa ,  Ramanujam Srinidhi Embar

IPC: H03F1/02 ,  H03F3/19 ,  H01P5/12 ,  H03F3/21

CPC classification number: H03F1/0288 ,  H01P5/12 ,  H03F1/07 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/451 ,  H03F2203/21142

Abstract: A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal carried by the first signal conduction path. A delay element is configured to impose a phase delay on the output signal of the first coupler to generate a delayed output signal. The device includes a second coupler coupled to the second signal conduction path. The second coupler is connected to the delay element and configured to inject the delayed output signal into the second signal conduction path.

公开(公告)号：US09337774B2

公开(公告)日：2016-05-10

申请号：US14491574

申请日：2014-09-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Margaret A. Szymanowski ,  L. M. Mahalingam ,  Sarmad K. Musa ,  Fernando A. Santos ,  Jerry L. White

IPC: H01L23/66 ,  H03F1/02 ,  H01L21/56 ,  H01L25/065 ,  H03F1/42 ,  H03F3/19 ,  H03F3/21 ,  H01L23/64

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/645 ,  H01L23/66 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48195 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03F1/0288 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/36 ,  H03F2200/451 ,  H01L2924/014 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of a packaged radio frequency (RF) device includes a device substrate with a voltage reference plane, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, a first transistor die coupled to a top surface of the device substrate with a solder bond, a second die coupled to the top surface of the device substrate with a conductive epoxy that electrically couples at least one component of the second die to the voltage reference plane, and non-conductive molding compound over the top surface of the device substrate and encompassing the first transistor die, the second die, a portion of the first input lead, and a portion of the first output lead.

Abstract translation: 封装射频（RF）器件的实施例包括具有电压参考平面的器件衬底，耦合到器件衬底的第一输入引线，耦合到器件衬底的第一输出引线，耦合到顶表面的第一晶体管管芯 具有焊接接合的器件衬底，第二管芯，其与导电环氧树脂耦合到器件衬底的顶表面，导电环氧树脂将第二管芯的至少一个部件电耦合到电压参考平面;以及非导电模塑料 并且包围第一晶体管管芯，第二管芯，第一输入引线的一部分和第一输出引线的一部分。

公开(公告)号：US09450547B2

公开(公告)日：2016-09-20

申请号：US14104870

申请日：2013-12-12

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Margaret A. Szymanowski ,  Sarmad K. Musa ,  Fernando A. Santos ,  Mahesh K. Shah

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/552 ,  H01L21/56 ,  H03F3/213 ,  H03F1/02 ,  H01L23/492

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件的系统和方法。 半导体器件具有基板，第一电路和第二电路在其上彼此靠近地形成。 导电材料的隔离壁位于第一电路和第二电路之间，隔离壁被配置为在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 介绍了几种类型的隔离墙。