发明申请
- 专利标题： MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS
- 专利标题（中）： 用于指导性设计的机构执行多个指令序列
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申请号： US15276290申请日： 2016-09-26
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公开(公告)号： US20170010895A1公开(公告)日： 2017-01-12
- 发明人: Hong Wang , John P. Shen , Edward T. Grochowski , Richard A. Hankins , Gautham N. Chinya , Bryant E. Bigbee , Shivnandan D. Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggarwal , Prashant Sethi , Baiju V. Patel , James P. Held
- 申请人： Intel Corporation
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F9/30 ; G06F9/48
摘要：
In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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