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    Migration of Trusted Security Attributes to a Security Engine Co-Processor
    3.
    发明申请
    Migration of Trusted Security Attributes to a Security Engine Co-Processor 审中-公开

    公开(公告)号：US20180004979A1

    公开(公告)日：2018-01-04

    申请号：US15200935

    申请日：2016-07-01

    申请人： Intel Corporation

    发明人： Jose S. Niell ,  Gautham N. Chinya ,  Khee Wooi Lee ,  William A. Stevens, JR. ,  Josh Triplett

    IPC分类号： G06F21/70

    摘要： A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.

    PREDICTOR FOR HARD-TO-PREDICT BRANCHES
    7.
    发明申请
    PREDICTOR FOR HARD-TO-PREDICT BRANCHES 审中-公开

    公开(公告)号：US20190004802A1

    公开(公告)日：2019-01-03

    申请号：US15637562

    申请日：2017-06-29

    申请人： Intel Corporation

    发明人： Stephen J. Tarsa ,  Gokce Keskin ,  Gautham N. Chinya ,  Hong Wang

    IPC分类号： G06F9/38 ,  G06N3/04

    摘要： A processor, including: an execution unit including branching circuitry; a branch predictor, including a hard-to-predict (HTP) branch filter to identify an HTP branch; and a special branch predictor to receive identification of an HTP branch from the HTP branch filter, the special branch predictor including a convolutional neural network (CNN) branch predictor to predict a branching action for the HTP branch.

    Prefetcher for delinquent irregular loads
    10.
    发明授权
    Prefetcher for delinquent irregular loads 有权

    公开(公告)号：US10713052B2

    公开(公告)日：2020-07-14

    申请号：US16021974

    申请日：2018-06-28

    申请人： Intel Corporation

    发明人： Karthik Sankaranarayanan ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Helia Naeimi

    IPC分类号： G06F9/38 ,  G06F9/30

    摘要： Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.