A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.