公开(公告)号：US10319732B2

公开(公告)日：2019-06-11

申请号：US15622497

申请日：2017-06-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC分类号： H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786

摘要： In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US09871050B1

公开(公告)日：2018-01-16

申请号：US15232906

申请日：2016-08-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC分类号： H01L29/788 ,  H01L27/11531 ,  H01L27/12 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11521

CPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1207 ,  H01L29/42328 ,  H01L29/42336

摘要： A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.

公开(公告)号：US09711513B2

公开(公告)日：2017-07-18

申请号：US14918048

申请日：2015-10-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

IPC分类号： H01L27/12 ,  H01L27/11524 ,  H01L27/11529 ,  H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

公开(公告)号：US20170077314A1

公开(公告)日：2017-03-16

申请号：US14853146

申请日：2015-09-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Elliot John Smith ,  Sven Beyer ,  Nigel Chan ,  Jan Hoentschel

IPC分类号： H01L29/792 ,  H01L29/06 ,  H01L21/326 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/7923 ,  H01L21/326 ,  H01L21/76254 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/665 ,  H01L29/66833

摘要： The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

摘要翻译： 本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘 结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。 半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

公开(公告)号：US09590118B1

公开(公告)日：2017-03-07

申请号：US14853146

申请日：2015-09-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Elliot John Smith ,  Sven Beyer ,  Nigel Chan ,  Jan Hoentschel

IPC分类号： H01L29/76 ,  H01L29/792 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762 ,  H01L21/326

CPC分类号： H01L29/7923 ,  H01L21/326 ,  H01L21/76254 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/665 ,  H01L29/66833

摘要： The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

摘要翻译： 本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘 结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。 半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

公开(公告)号：US20140256137A1

公开(公告)日：2014-09-11

申请号：US13793082

申请日：2013-03-11

申请人： GLOBALFOUNDRIES INC.

发明人： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

摘要翻译： 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。

公开(公告)号：US20180108668A1

公开(公告)日：2018-04-19

申请号：US15831833

申请日：2017-12-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/12

CPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1207 ,  H01L29/42328 ,  H01L29/42336

摘要： An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

公开(公告)号：US20170125432A1

公开(公告)日：2017-05-04

申请号：US14982228

申请日：2015-12-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Ralf Richter ,  Sven Beyer

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L27/11531 ,  H01L21/28273 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/0649 ,  H01L29/42328

摘要： A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.

公开(公告)号：US09608112B2

公开(公告)日：2017-03-28

申请号：US14816337

申请日：2015-08-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC分类号： H01L27/01 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

摘要： The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

公开(公告)号：US20170047336A1

公开(公告)日：2017-02-16

申请号：US14918048

申请日：2015-10-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

IPC分类号： H01L27/115 ,  H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

摘要翻译： 半导体结构包括设置在半导体材料中的包括源极区，沟道区和漏极区的非易失性存储单元。 沟道区域包括邻近源极区域的第一部分和沟道区域的第一部分与漏极区域之间的第二部分。 在沟道区域的第一部分之上提供电绝缘的浮动栅极。 非易失性存储单元还包括选择栅极和控制栅极。 选择栅极的第一部分设置在沟道区域的第二部分上。 选择栅极的第二部分设置在与选择栅极的第一部分相邻的浮置栅极的一部分上。 控制栅极设置在浮动栅极上并且邻近选择栅极的第二部分。