Invention Application
- Patent Title: APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAGE REGULATOR
- Patent Title (中): 降低集成电压调节器功率损耗的装置和方法
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Application No.: US14836780Application Date: 2015-08-26
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Publication No.: US20170060205A1Publication Date: 2017-03-02
- Inventor: Krishna Bharath , Srikrishnan Venkataraman , William J. Lambert , Michael J. Hill , Alexander Slepoy , Dong Zhong , Kaladhar Radhakrishnan , Hector A. Aguirre Diaz , Jonathan P. Douglas
- Applicant: Intel Corporation
- Main IPC: G06F1/26
- IPC: G06F1/26 ; H02J1/00 ; G06F1/32 ; H02M3/158

Abstract:
Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
Public/Granted literature
- US09753510B2 Apparatus and method to reduce power losses in an integrated voltage regulator Public/Granted day:2017-09-05
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