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公开(公告)号：US10541615B1
公开(公告)日：2020-01-21
申请号：US16021712
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Amit Jain , Sameer Shekhar , Alexander Lyakhov , Jonathan P. Douglas , Vivek Saxena
IPC: H02M3/158
Abstract: Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.
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公开(公告)号：US09065470B2
公开(公告)日：2015-06-23
申请号：US13720462
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Takao Oshita , George L. Geannopoulos , David E. Duarte , J Keith Hodgson , James S. Ayers , Avner Kornfeld , Jonathan P. Douglas
IPC: H03M3/00
CPC classification number: H03M3/458 , H03M1/00 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/1245 , H03M1/804 , H03M3/30 , H03M3/32 , H03M3/34
Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
Abstract translation: 描述了一种模数转换器（ADC），其包括：用于接收模拟信号的Σ-Δ调制器，可用于执行斩波以消除共模噪声的Σ-Δ调制器; 以及耦合到Σ-Δ调制器的一个或多个计数器以产生表示模拟信号的数字代码。
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公开(公告)号：US09753510B2
公开(公告)日：2017-09-05
申请号：US14836780
申请日：2015-08-26
Applicant: Intel Corporation
Inventor： Krishna Bharath , Srikrishnan Venkataraman , William J. Lambert , Michael J. Hill , Alexander Slepoy , Dong Zhong , Kaladhar Radhakrishnan , Hector A. Aguirre Diaz , Jonathan P. Douglas
CPC classification number: G06F1/26 , G06F1/3203 , H01L23/645 , H02J1/00 , H02M3/158 , H02M3/1584 , H02M2001/008 , H02M2003/1586
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
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公开(公告)号：US09696350B2
公开(公告)日：2017-07-04
申请号：US13907802
申请日：2013-05-31
Applicant: INTEL CORPORATION
Inventor： Edward A. Burton , Gerhard Schrom , Michael W. Rogers , Alexander Lyakhov , Ravi Sankar Vunnam , Jonathan P. Douglas , Fabrice Paillet , J. Keith Hodgson , William Dawson Kesling , Chiu Keung Tang , Narayanan Raghuraman , Narayanan Natarajan , Samie Samaan , George Geannopoulos
IPC: H02M3/157 , G01R19/00 , H03L5/00 , H03M1/66 , G06T3/40 , H02M3/156 , H02M1/088 , H02M3/158 , H03M1/68 , H02M1/00
CPC classification number: G01R19/0092 , G06T3/40 , H02M1/088 , H02M3/156 , H02M3/157 , H02M3/158 , H02M2001/0009 , H02M2003/1566 , H03L5/00 , H03M1/66 , H03M1/685
Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.
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公开(公告)号：US09520895B2
公开(公告)日：2016-12-13
申请号：US14705805
申请日：2015-05-06
Applicant: Intel Corporation
Inventor： Takao Oshita , George L. Geannopoulos , David E. Duarte , J Keith Hodgson , James S. Ayers , Avner Kornfeld , Jonathan P. Douglas
CPC classification number: H03M3/458 , H03M1/00 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/1245 , H03M1/804 , H03M3/30 , H03M3/32 , H03M3/34
Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
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Patent Agency Ranking
公开(公告)号：US20160233879A1
公开(公告)日：2016-08-11
申请号：US14705805
申请日：2015-05-06
Applicant: Intel Corporation
Inventor： Takao Oshita , George L. Geannopoulos , David E. Duarte , J. Keith Hodgson , James S. Ayers , Avner Kornfeld , Jonathan P. Douglas
CPC classification number: H03M3/458 , H03M1/00 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/1245 , H03M1/804 , H03M3/30 , H03M3/32 , H03M3/34
Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
Abstract translation: 描述了一种模数转换器（ADC），其包括：用于接收模拟信号的Σ-Δ调制器，可用于执行斩波以消除共模噪声的Σ-Δ调制器; 以及耦合到Σ-Δ调制器的一个或多个计数器以产生表示模拟信号的数字代码。
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7.发明授权公开(公告)号：US11437294B2
公开(公告)日：2022-09-06
申请号：US16059513
申请日：2018-08-09
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit Kumar Jain , Kaladhar Radhakrishnan , Jonathan P. Douglas , Chin Lee Kuan
IPC: H01L23/367 , H01L23/498 , H01L23/522 , H01L23/00 , G06F1/20
Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.
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公开(公告)号：US10796977B2
公开(公告)日：2020-10-06
申请号：US16292218
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： John Fallin , Daniel J. Ragland , Jonathan P. Douglas
IPC: H05K7/00 , H05K7/20 , H01L23/34 , H01L23/367 , H01L23/467 , H01L23/473 , G06F1/20 , G06F1/26 , G06F17/50 , G11C5/00 , G11C29/50 , G06F11/14
Abstract: Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.
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公开(公告)号：US10404152B2
公开(公告)日：2019-09-03
申请号：US15721314
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Srikrishnan Venkataraman , Sreedhar Narayanaswamy , Jonathan P. Douglas , Chih-Chung Jonathan Wei , Ankush Varma , Narayanan Natarajan
Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.
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10.发明申请公开(公告)号：US20190103801A1
公开(公告)日：2019-04-04
申请号：US15721314
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Srikrishnan Venkataraman , Sreedhar Narayanaswamy , Jonathan P. Douglas , Chih-Chung Jonathan Wei , Ankush Varma , Narayanan Natarajan
CPC classification number: H02M1/00 , G06F1/26 , H02M3/158 , H02M3/33561 , H02M2001/0009 , H02M2001/0012 , H02M2001/008 , H03L7/099
Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.
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