Invention Application
US20170069591A1 WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIBUTION LAYER
有权
在重新分配层的位置使用线束焊接的水平包装
- Patent Title: WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIBUTION LAYER
- Patent Title (中): 在重新分配层的位置使用线束焊接的水平包装
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Application No.: US15357553Application Date: 2016-11-21
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Publication No.: US20170069591A1Publication Date: 2017-03-09
- Inventor: Rajesh Katkar , Tu Tam Vu , Bongsub Lee , Kyong-Mo Bang , Xuan Li , Long Huynh , Gabriel Z. Guevara , Akash Agrawal , Willmar Subido , Laura Wills Mirkarimi
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L21/78 ; H01L25/10 ; H01L23/31 ; H01L21/56

Abstract:
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
Public/Granted literature
- US10008469B2 Wafer-level packaging using wire bond wires in place of a redistribution layer Public/Granted day:2018-06-26
Information query
IPC分类: