Invention Application
- Patent Title: METHOD OF FABRICATING A GATE CAP LAYER
-
Application No.: US15081932Application Date: 2016-03-27
-
Publication No.: US20170162396A1Publication Date: 2017-06-08
- Inventor: Fu-Shou Tsai , Yu-Ting Li , Chih-Hsun Lin , Li-Chieh Hsu , Yi-Liang Liu , Po-Cheng Huang , Kun-Ju Li , Wen-Chin Lin
- Applicant: UNITED MICROELECTRONICS CORP.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/02 ; H01L21/3105 ; H01L29/66

Abstract:
A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.
Public/Granted literature
- US09972498B2 Method of fabricating a gate cap layer Public/Granted day:2018-05-15
Information query
IPC分类: