公开(公告)号：US10192826B2

公开(公告)日：2019-01-29

申请号：US15853978

申请日：2017-12-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC分类号： H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US09966263B1

公开(公告)日：2018-05-08

申请号：US15587228

申请日：2017-05-04

申请人： United Microelectronics Corp.

发明人： Kun-Ju Li ,  Li-Chieh Hsu ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Chih-Hsun Lin ,  Hsin-Jung Liu

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

摘要： A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

公开(公告)号：US09905430B1

公开(公告)日：2018-02-27

申请号：US15245194

申请日：2016-08-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/84 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC分类号： H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

摘要： A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US20180033633A1

公开(公告)日：2018-02-01

申请号：US15220365

申请日：2016-07-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

摘要： A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US09230912B2

公开(公告)日：2016-01-05

申请号：US14279602

申请日：2014-05-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hsin-Kuo Hsu ,  Li-Chieh Hsu ,  Hsiang-Hao Chen ,  Chung-Wei Hsueh

IPC分类号： H01L21/311 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321

CPC分类号： H01L23/528 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches.

摘要翻译： 提供一种制造半导体器件的方法和使用其制造的器件。 根据本实施例，提供了形成有电介质层的基板。 在电介质层中限定多个沟槽，并且通过电介质层隔离沟槽。 在沟槽中形成第一阻挡层作为沟槽的阻挡层，然后用导体填充沟槽。 然后，沟槽中的导体被部分地去除以形成多个凹槽，其中保留的导体具有平坦的表面。 接下来，在凹槽中形成第二阻挡层作为沟槽的阻挡盖。

公开(公告)号：US20180061656A1

公开(公告)日：2018-03-01

申请号：US15245194

申请日：2016-08-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC分类号： H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

摘要： A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US09875909B1

公开(公告)日：2018-01-23

申请号：US15220365

申请日：2016-07-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/306

CPC分类号： H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

摘要： A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US10103034B2

公开(公告)日：2018-10-16

申请号：US15678134

申请日：2017-08-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC分类号： H01L21/3105 ,  H01L29/06 ,  H01L29/78

摘要： A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20180138125A1

公开(公告)日：2018-05-17

申请号：US15853978

申请日：2017-12-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC分类号： H01L23/528 ,  H01L29/417 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US20180012772A1

公开(公告)日：2018-01-11

申请号：US15678134

申请日：2017-08-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC分类号： H01L21/3105 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

摘要： A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.