Invention Application
- Patent Title: SYSTEMS, METHODS AND DEVICES FOR USING THERMAL MARGIN OF A CORE IN A PROCESSOR
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Application No.: US15086456Application Date: 2016-03-31
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Publication No.: US20170285700A1Publication Date: 2017-10-05
- Inventor: Daniel G. Cartagena , Corey D. Gough , Vivek Garg , Nikhil Gupta
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F1/20
- IPC: G06F1/20 ; G06F1/30 ; G06F1/28

Abstract:
A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.
Public/Granted literature
- US10474208B2 Systems, methods and devices for using thermal margin of a core in a processor Public/Granted day:2019-11-12
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