公开(公告)号：US10474208B2

公开(公告)日：2019-11-12

申请号：US15086456

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Daniel G. Cartagena ,  Corey D. Gough ,  Vivek Garg ,  Nikhil Gupta

IPC: G06F1/20 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

公开(公告)号：US20170285700A1

公开(公告)日：2017-10-05

申请号：US15086456

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Daniel G. Cartagena ,  Corey D. Gough ,  Vivek Garg ,  Nikhil Gupta

IPC: G06F1/20 ,  G06F1/30 ,  G06F1/28

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

公开(公告)号：US20190171263A1

公开(公告)日：2019-06-06

申请号：US16269285

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Casey R. Winkel ,  Daniel G. Cartagena

IPC: G06F1/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: Systems, apparatuses, methods, and computer-readable media, for a computing platform including a controller to manage an amount of power supplied to a processor core. The processor core operates in a first operation mode consuming a first power level, and in a second operation mode consuming a second power level higher than the first power level. The controller is to reduce or cause to be reduced an amount of power supplied to a component of a thermal energy management solution for a time period from a third power level to a fourth power level lower than the third power level, while increasing or causing to be increased an amount of power supplied to the processor core for the processor core to operate in the second operation mode at the second power level during but not exceed the time period. Other embodiments may be described and/or claimed.