公开(公告)号：US11703906B2

公开(公告)日：2023-07-18

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20180004620A1

公开(公告)日：2018-01-04

申请号：US15705854

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Jonathan D. Combs ,  Michael W. Chynoweth ,  Jason W. Brandt ,  Corey D. Gough

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments disclosed herein provide for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to track a non-precise event and to increment upon occurrence of the non-precise event, wherein the non-precise event comprises a first type of performance event that is not linked to an instruction in an instruction trace. The processing device also includes a first handler circuit to generate and store a first record, the first record comprising architectural metadata defining a state of the processing device at a time of generation of the first record, wherein the first handler circuit to generate records corresponding to precise events. The processing device further includes a second handler circuit communicably coupled to the first handler circuit, the second handler circuit to cause the first handler circuit to generate a second record for the non-precise event upon overflow of the performance counter.

公开(公告)号：US20180365022A1

公开(公告)日：2018-12-20

申请号：US15625423

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Vasudevan Srinivasan ,  Eliezer Weissmann ,  Stephen H. Gunther ,  Eugene Gorbatov ,  Russell J. Fenger ,  Guy M. Therien

IPC: G06F9/44 ,  G06F3/06

Abstract: Embodiments of processors, methods, and systems for dynamic offlining and onlining of processor cores are described. In an embodiment, a processor includes a plurality of cores, a core status storage location, and a core tracker. Core status information for at least one of the plurality of cores is the be stored in the core status storage location. The core status information is to include a core state to be used by a software scheduler. The core state is to be one of a plurality of core state values including an online value, a requesting-to-go-offline value, and an offline value. The core tracker is to track usage of the at least one core and to change the core state from the online value to the requesting-to-go-offline value in response to determining that usage has reached a predetermined threshold.

公开(公告)号：US09880601B2

公开(公告)日：2018-01-30

申请号：US14582741

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Corey D. Gough ,  Ian M. Steiner ,  Krishnakanth V. Sistla

IPC: G06F1/28 ,  G06F13/42

CPC classification number: G06F1/28 ,  G06F1/3228 ,  G06F13/4282 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

公开(公告)号：US20170285700A1

公开(公告)日：2017-10-05

申请号：US15086456

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Daniel G. Cartagena ,  Corey D. Gough ,  Vivek Garg ,  Nikhil Gupta

IPC: G06F1/20 ,  G06F1/30 ,  G06F1/28

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

公开(公告)号：US11169560B2

公开(公告)日：2021-11-09

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris Macnamara ,  John J. Browne ,  Ripan Das

IPC: G06G1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324 ,  G06F1/08

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US10509455B2

公开(公告)日：2019-12-17

申请号：US15860300

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Corey D. Gough ,  Ian M. Steiner ,  Krishnakanth V. Sistla

IPC: G06F1/28 ,  G06F13/42 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3287

Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

公开(公告)号：US09766999B2

公开(公告)日：2017-09-19

申请号：US14292140

申请日：2014-05-30

Applicant: Intel Corporation

Inventor： Jonathan D. Combs ,  Michael W. Chynoweth ,  Jason W. Brandt ,  Corey D. Gough

IPC: G06F11/00 ,  G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.

公开(公告)号：US20160187952A1

公开(公告)日：2016-06-30

申请号：US14582741

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Corey D. Gough ,  Ian M. Steiner ,  Krishnakanth V. Sistla

IPC: G06F1/28 ,  G06F13/42

CPC classification number: G06F1/28 ,  G06F1/3228 ,  G06F13/4282 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

Abstract translation: 提供了一种用于控制链接的方法。 这可以包括确定耦合到链路的第一设备的状况，在第一设备处从耦合到链路的第二设备接收对特定链路状态的请求，以及基于所确定的链路来确定链路的功率状态 第一个设备的状态。