Invention Application
- Patent Title: BITCELL STATE RETENTION
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Application No.: US15495936Application Date: 2017-04-24
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Publication No.: US20170337958A1Publication Date: 2017-11-23
- Inventor: Charles AUGUSTINE , Shigeki TOMISHIMA , James W. TSCHANZ , Shih-Lien L. LU
- Applicant: INTEL CORPORATION
- Main IPC: G11C11/16
- IPC: G11C11/16

Abstract:
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
Public/Granted literature
- US10600462B2 Bitcell state retention Public/Granted day:2020-03-24
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