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    BITCELL STATE RETENTION
    1.
    发明申请
    BITCELL STATE RETENTION 审中-公开

    公开(公告)号：US20170337958A1

    公开(公告)日：2017-11-23

    申请号：US15495936

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

    IPC: G11C11/16

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

    NEAREST NEIGHBOR SEARCH LOGIC CIRCUIT WITH REDUCED LATENCY AND POWER CONSUMPTION
    4.
    发明申请
    NEAREST NEIGHBOR SEARCH LOGIC CIRCUIT WITH REDUCED LATENCY AND POWER CONSUMPTION 审中-公开

    公开(公告)号：US20200183922A1

    公开(公告)日：2020-06-11

    申请号：US16795516

    申请日：2020-02-19

    Applicant: Intel Corporation

    Inventor： Wootaek LIM ,  Minchang CHO ,  Somnath PAUL ,  Charles AUGUSTINE ,  Suyoung BANG ,  Turbo MAJUMDER ,  Muhammad M. KHELLAH

    IPC: G06F16/2453 ,  G06F7/08 ,  G06F7/20 ,  G11C15/04

    Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit. The compare and sort circuit is to identify k nearest ones of the data items whose hashes were selected by the content addressable memory.

    CLUSTERING EVENTS IN A CONTENT ADDRESSABLE MEMORY
    5.
    发明申请
    CLUSTERING EVENTS IN A CONTENT ADDRESSABLE MEMORY 审中-公开

    公开(公告)号：US20190043583A1

    公开(公告)日：2019-02-07

    申请号：US16110990

    申请日：2018-08-23

    Applicant: INTEL CORPORATION

    Inventor： Turbo MAJUMDER ,  Somnath PAUL ,  Charles AUGUSTINE ,  Muhammad M. KHELLAH

    IPC: G11C15/04 ,  G11C8/10 ,  G06F17/30 ,  G06T1/60

    Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.

    SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY
    8.
    发明公开
    SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY 审中-公开

    公开(公告)号：US20230284427A1

    公开(公告)日：2023-09-07

    申请号：US17686241

    申请日：2022-03-03

    Applicant: Intel Corporation

    Inventor： Charles AUGUSTINE ,  Seenivasan SUBRAMANIAM ,  Patrick MORROW ,  Muhammad M. KHELLAH

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

    Abstract: Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

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