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    DYNAMIC SWITCH FOR MEMORY DEVICES
    1.
    发明公开
    DYNAMIC SWITCH FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240028531A1

    公开(公告)日：2024-01-25

    申请号：US18375472

    申请日：2023-09-30

    Applicant: Intel Corporation

    Inventor： John R. DREW ,  James A. McCALL ,  Tongyan ZHAI ,  Jun LIAO ,  Min Suet LIM ,  Shigeki TOMISHIMA

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1694 ,  G06F13/1689 ,  G06F13/4022

    Abstract: A memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. Dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. A switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. A memory controller can toggle a chip select signal as a single control signal to drive the switch. Each switch includes pairs of field effect transistors (FETs), including any of CMOS, NMOS and PMOS FETs. The switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.

    SUPPLY-SWITCHED DUAL CELL MEMORY BITCELL
    2.
    发明申请
    SUPPLY-SWITCHED DUAL CELL MEMORY BITCELL 审中-公开

    公开(公告)号：US20170345477A1

    公开(公告)日：2017-11-30

    申请号：US15648413

    申请日：2017-07-12

    Applicant: INTEL CORPORATION

    Inventor： Shigeki TOMISHIMA

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: In one embodiment, a bit state in a supply-switched dual cell memory bitcell in accordance with the present description, may be read by coupling a supply line to a common node of the bitcell to drive complementary currents through complementary resistance state storage cells for a pair of complementary bit line signal lines of the bitcell. The bit state of the bitcell may be read by sensing complementary bit state signals on the pair of first and second complementary bit line signal lines. In one embodiment, each resistance state storage cell has a resistance state ferromagnetic device such as a magnetic-tunneling junction (MTJ). In one embodiment, a supply-switched dual cell memory bitcell in accordance with the present description may lack a source or select line (SL) signal line. Other aspects are described herein.

    STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I/OS)
    4.
    发明申请
    STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I/OS) 有权

    公开(公告)号：US20210335393A1

    公开(公告)日：2021-10-28

    申请号：US17372298

    申请日：2021-07-09

    Applicant: Intel Corporation

    Inventor： Chong J. ZHAO ,  Shigeki TOMISHIMA ,  Kuljit S. BAINS ,  James A. McCALL ,  Dimitrios ZIAKAS

    IPC: G11C5/06

    Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

    BITCELL STATE RETENTION
    6.
    发明申请
    BITCELL STATE RETENTION 审中-公开

    公开(公告)号：US20170337958A1

    公开(公告)日：2017-11-23

    申请号：US15495936

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

    IPC: G11C11/16

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

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