Invention Application
- Patent Title: STACKED-GATE SUPER-JUNCTION MOSFET
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Application No.: US15224835Application Date: 2016-08-01
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Publication No.: US20180012994A1Publication Date: 2018-01-11
- Inventor: Gary H. LOECHELT , Gordon M. GRIVNA
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/36 ; H01L29/06 ; H01L29/66 ; H01L21/265

Abstract:
A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.
Public/Granted literature
- US09859419B1 Stacked-gate super-junction MOSFET Public/Granted day:2018-01-02
Information query
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