公开(公告)号：US20180294332A1

公开(公告)日：2018-10-11

申请号：US15481523

申请日：2017-04-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66568 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7823 ,  H01L29/7825

Abstract: An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.

公开(公告)号：US20180012994A1

公开(公告)日：2018-01-11

申请号：US15224835

申请日：2016-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7827 ,  H01L21/26513 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/36 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7811 ,  H01L29/7813

Abstract: A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

公开(公告)号：US20190386129A1

公开(公告)日：2019-12-19

申请号：US16009484

申请日：2018-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Wonhwa LEE ,  Gary H. LOECHELT

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/10 ,  H01L29/06 ,  H01L29/739 ,  H01L21/306 ,  H01L29/47 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66

Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

公开(公告)号：US20170062610A1

公开(公告)日：2017-03-02

申请号：US14837228

申请日：2015-08-27

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Ladislav SELIGA ,  Thierry Coffi Herve YAO ,  Jaroslav PJENCÁK ,  Gary H. LOECHELT

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/761 ,  H01L21/823412 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Abstract translation: 电子器件可以包括具有主表面的半导体层，与主表面相邻的漂移区域，与漂移区域相邻并且与漂移区域相比更深地延伸到半导体层中的漏极区域， 主表面，覆盖漏极区域的绝缘层，以及延伸穿过绝缘层到漏极区域的接触。 在一个实施例中，漏极区域可以包括沉降片区域，其允许在过电压事件期间发生裸露区域的体破坏，其中体积击穿发生在漂移区域外部，并且在特定实施例中，远离浅沟槽隔离 结构或其他敏感结构。

公开(公告)号：US20200251588A1

公开(公告)日：2020-08-06

申请号：US16451288

申请日：2019-06-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT ,  Jaume ROIG-GUITART

IPC: H01L29/78 ,  H01L29/66

Abstract: Systems and methods of the disclosed embodiments include a semiconductor device that includes an N-doped pillar with a gate structure configured to control a signal between a drain and a source in response to a gate voltage signal. The semiconductor device may also include a P-doped pillar with a capacitive structure. The capacitive structure capacitively couples the P-doped pillar to the gate structure to reduce ringing in the gate voltage signal.

公开(公告)号：US20200098857A1

公开(公告)日：2020-03-26

申请号：US16141761

申请日：2018-09-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA ,  Jaegil LEE ,  MinKyung KO ,  Youngchul CHOI

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/225 ,  H01L21/764 ,  H01L29/78

Abstract: A transistor device includes an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate. An isolation structure is disposed in a trench between the n-doped pillar and the p-doped pillar, and a source and a gate are disposed on the n-doped pillar. The isolation structure can include an air gap encapsulated in the trench by an oxide plug. The isolation structure can include an epi liner disposed on surfaces of the n-doped pillar and the p-doped pillar.

公开(公告)号：US20170062410A1

公开(公告)日：2017-03-02

申请号：US14841530

申请日：2015-08-31

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT

IPC: H01L27/06 ,  H01L29/866 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L49/02 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/0733 ,  H01L28/60 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/866 ,  H01L29/872 ,  H03K17/08142

Abstract: A circuit can include a transistor, a capacitive element, and a rectifying element. The rectifying element and the capacitive element can be serially connected and coupled to the current-carrying terminals of the transistor. An electronic device may include part of the circuit. The electronic device can include a diode that includes a horizontally-oriented semiconductor member and a vertically-oriented semiconductor member having different conductivity types. The ends of the horizontally-oriented semiconductor and vertically-oriented semiconductor members physically contact each other. A process of forming an electronic device can include forming a semiconductor layer and forming a second semiconductor member. In a finished device, a diode includes a junction between dopants of first and second conductivity types within the semiconductor layer, within the semiconductor member, or at an interface between the semiconductor layer and the semiconductor member.

Abstract translation: 电路可以包括晶体管，电容元件和整流元件。 整流元件和电容元件可以串联连接并耦合到晶体管的载流端子。 电子设备可以包括电路的一部分。 电子器件可以包括二极管，其包括水平取向的半导体部件和具有不同导电类型的垂直取向的半导体部件。 水平取向的半导体和垂直取向的半导体部件的端部彼此物理接触。 形成电子器件的工艺可以包括形成半导体层并形成第二半导体部件。 在成品器件中，二极管包括在半导体层内，半导体元件内或半导体层与半导体元件之间的界面处的第一和第二导电类型的掺杂剂之间的结。

公开(公告)号：US20200273981A1

公开(公告)日：2020-08-27

申请号：US16871268

申请日：2020-05-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Wonhwa LEE ,  Gary H. LOECHELT

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/739 ,  H01L21/306 ,  H01L29/47 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L29/872

Abstract: A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

公开(公告)号：US20140264574A1

公开(公告)日：2014-09-18

申请号：US14168423

申请日：2014-01-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66659 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835

Abstract: An electronic device can include different vertical conductive structures that can be formed at different times. The vertical conductive structures can have the same or different shapes. In an embodiment, an insulating spacer can be used to help electrically insulate a particular vertical conductive structure from another part of the workpiece, and an insulating spacer may not be used to electrically isolate a different vertical conductive structure. The vertical conductive structures can be tailored for particular electrical considerations or to a process flow when formation of other electronic components may also be formed within either or both of the particular vertical conductive structures.

Abstract translation: 电子设备可以包括可以在不同时间形成的不同的垂直导电结构。 垂直导电结构可具有相同或不同的形状。 在一个实施例中，可以使用绝缘间隔件来帮助将特定的垂直导电结构与工件的另一部分电绝缘，并且可以不使用绝缘间隔件来电隔离不同的垂直导电结构。 垂直导电结构可以针对特定的电学考虑或者在其它电子部件的形成也可以形成在特定的垂直导电结构中的任一个或两者内的过程流程。

公开(公告)号：US20140103424A1

公开(公告)日：2014-04-17

申请号：US14106504

申请日：2013-12-13

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT ,  Prasad VENKATRAMAN

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7827 ,  H01L29/7835

Abstract: An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.

Abstract translation: 电子器件可以包括包括下面的掺杂区域和覆盖衬底的半导体层的衬底。 沟槽可以具有侧壁并且至少部分地延伸穿过半导体层。 电子器件还可以包括邻近下面的掺杂区域的第一导电结构，绝缘层和沟槽内的第二导电结构。 绝缘层可以设置在第一和第二导电结构之间，并且第一导电结构可以设置在绝缘层和下面的掺杂区域之间。 可以执行形成电子器件的工艺，使得第一导电结构包括导电填充材料或半导体层内的掺杂区域。 第一导电结构可以允许下面的掺杂区域离沟道区域更远，并允许给定BVDSS的RDSON较低。