Invention Application
- Patent Title: TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS
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Application No.: US15664158Application Date: 2017-07-31
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Publication No.: US20180033754A1Publication Date: 2018-02-01
- Inventor: Roger Dugas , John Trezza
- Applicant: Cufer Asset Ltd. L.L.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L25/18 ; H01L25/065 ; H01L23/66 ; H01L23/552 ; H01L23/538 ; H01L23/498 ; H01L23/488 ; H01L23/48 ; H01L23/427 ; H01L21/768 ; H01L21/683 ; H01L25/00 ; H01S5/042 ; H01S5/183 ; H01S5/022

Abstract:
A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
Public/Granted literature
- US10340239B2 Tooling for coupling multiple electronic chips Public/Granted day:2019-07-02
Information query
IPC分类: