A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.