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公开(公告)号：US20180130538A1
公开(公告)日：2018-05-10
申请号：US15862397
申请日：2018-01-04
CPC分类号： G11C16/26 , G11C7/12 , G11C7/18 , G11C16/0408 , G11C16/08 , G11C16/24 , G11C16/28 , G11C2207/002 , G11C2207/12
摘要： A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.
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公开(公告)号：US09966145B2
公开(公告)日：2018-05-08
申请号：US15605708
申请日：2017-05-25
摘要： A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.
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公开(公告)号：US09767907B2
公开(公告)日：2017-09-19
申请号：US15083056
申请日：2016-03-28
摘要： A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.
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公开(公告)号：US20170084334A1
公开(公告)日：2017-03-23
申请号：US15083056
申请日：2016-03-28
摘要： A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.
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公开(公告)号：US08982612B2
公开(公告)日：2015-03-17
申请号：US13888593
申请日：2013-05-07
CPC分类号： G11C13/0028 , G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.
摘要翻译： 用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。 该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。 行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。 行解码器可以包括耦合到全局预编码阶段的行解码器级。 行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号 信号和偏置信号。
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公开(公告)号：US10818368B2
公开(公告)日：2020-10-27
申请号：US16294386
申请日：2019-03-06
IPC分类号： G11C8/08 , G11C16/34 , G11C5/14 , G11C16/20 , H03K19/00 , H03K19/0175 , G11C8/06 , G11C13/00 , H03K19/0185 , G11C8/10
摘要： A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US20190287633A1
公开(公告)日：2019-09-19
申请号：US16294386
申请日：2019-03-06
摘要： A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US10249373B2
公开(公告)日：2019-04-02
申请号：US15862397
申请日：2018-01-04
摘要： A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.
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公开(公告)号：US20180108405A1
公开(公告)日：2018-04-19
申请号：US15842347
申请日：2017-12-14
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C17/18 , G11C2013/0042
摘要： A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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公开(公告)号：US09679655B2
公开(公告)日：2017-06-13
申请号：US15140770
申请日：2016-04-28
摘要： A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.
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