Invention Application
- Patent Title: METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
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Application No.: US15730542Application Date: 2017-10-11
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Publication No.: US20180047846A1Publication Date: 2018-02-15
- Inventor: Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
- Applicant: INTEL CORPORATION
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/161 ; H01L29/165 ; H01L29/24 ; H01L29/08 ; H01L29/423 ; H01L29/49 ; H01L29/66 ; H04B1/3827 ; H01L29/06 ; H01L29/10 ; H01L29/267
Abstract:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Public/Granted literature
- US10367093B2 Method for fabricating transistor with thinned channel Public/Granted day:2019-07-30
Information query
IPC分类:
