Invention Application
- Patent Title: PROVIDING MEMORY BANDWIDTH COMPRESSION IN CHIPKILL-CORRECT MEMORY ARCHITECTURES
-
Application No.: US15266723Application Date: 2016-09-15
-
Publication No.: US20180074893A1Publication Date: 2018-03-15
- Inventor: Natarajan Vaidhyanathan , Luther James Blackwood , Mattheus Cornelis Antonius Adrianus Heddes , Michael Raymond Trombley , Colin Beaton Verrilli
- Applicant: QUALCOMM Incorporated
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C29/52 ; G06F3/06 ; H03M13/00

Abstract:
Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.
Public/Granted literature
- US10236917B2 Providing memory bandwidth compression in chipkill-correct memory architectures Public/Granted day:2019-03-19
Information query