公开(公告)号：US09710324B2

公开(公告)日：2017-07-18

申请号：US14857491

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Michael Raymond Trombley

IPC: G06F11/10 ,  H03M13/17

CPC classification number: G06F11/1012 ,  H03M13/17

Abstract: A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.

公开(公告)号：US10236917B2

公开(公告)日：2019-03-19

申请号：US15266723

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Natarajan Vaidhyanathan ,  Luther James Blackwood ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Michael Raymond Trombley ,  Colin Beaton Verrilli

IPC: H03M13/00 ,  G11C29/52 ,  G06F3/06 ,  H03M7/30 ,  G06F11/10

Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.

公开(公告)号：US20180074893A1

公开(公告)日：2018-03-15

申请号：US15266723

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Natarajan Vaidhyanathan ,  Luther James Blackwood ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Michael Raymond Trombley ,  Colin Beaton Verrilli

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/00

CPC classification number: H03M13/6312 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1012 ,  G11C29/52 ,  G11C2207/102 ,  H03M7/6041

Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.

公开(公告)号：US20160224241A1

公开(公告)日：2016-08-04

申请号：US14844516

申请日：2015-09-03

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Brian Joel Schuh ,  Michael Raymond Trombley ,  Natarajan Vaidhyanathan

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using back-to-back read operations by compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from error correcting code (ECC) bits of a first memory block in a memory line associated with the physical address. Based on the CI, the CMC determines whether the first memory block comprises compressed data. If not, the CMC performs a back-to-back read of one or more additional memory blocks of the memory line in parallel with returning the first memory block. Some aspects may further improve memory access latency by writing compressed data to each of a plurality of memory blocks of the memory line, rather than only to the first memory block.

Abstract translation: 公开了使用基于中央处理单元（CPU）的系统中的压缩存储器控制器（CMC）的背靠背读取操作来提供存储器带宽压缩。 在这方面，在一些方面，CMC被配置为接收对系统存储器中的物理地址的存储器读取请求，并且从第一个的第一个的错误校正码（ECC）位读取物理地址的压缩指示符（CI） 与物理地址相关联的内存条中的内存块。 基于CI，CMC确定第一存储块是否包含压缩数据。 如果不是，则CMC返回第一个存储器块，并行执行对存储器线的一个或多个附加存储器块的背对背读取。 一些方面可以通过将压缩数据写入到存储器线的多个存储块中的每一个而不是仅对第一存储器块来进一步改善存储器访问等待时间。

公开(公告)号：US20160224414A1

公开(公告)日：2016-08-04

申请号：US14857491

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Michael Raymond Trombley

IPC: G06F11/10 ,  H03M13/17

CPC classification number: G06F11/1012 ,  H03M13/17

Abstract: A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.

Abstract translation: 支持专用于存储ECC的纠错码（ECC）存储单元中的数据指示符的存储的双列直插存储器模块（DIMM）。 DIMM被配置为提供在突发数据存储单元中条带化的突发ECC存储单元。 DIMM被配置为在写入操作的写入数据地址上跨突发数据字存储单元对接收到的突发数据字进行条带化。 DIMM还被配置为以比在突发ECC存储单元中的数据位单元的数量少的比特在写入数据地址上跨突发ECC存储单元对突发数据字的接收突发ECC字进行条带化。 以这种方式，DIMM可以在突发ECC存储单元中的额外的剩余位中存储用于突发数据字的至少一个数据指示符。