Invention Application
- Patent Title: System and Method for Providing 3D Wafer Assembly With Known-Good-Dies
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Application No.: US15834658Application Date: 2017-12-07
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Publication No.: US20180096973A1Publication Date: 2018-04-05
- Inventor: Hong Shen , Liang Wang , Guilian Gao
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L21/768 ; H01L21/3105 ; H01L21/304 ; H01L21/306 ; H01L25/00 ; H01L21/683 ; H01L21/78 ; H01L21/56

Abstract:
Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.
Public/Granted literature
- US10515926B2 System and method for providing 3D wafer assembly with known-good-dies Public/Granted day:2019-12-24
Information query
IPC分类: