- 专利标题: METHOD OF FABRICATING PACKAGING LAYER OF FAN-OUT CHIP PACKAGE
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申请号: US15876210申请日: 2018-01-22
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公开(公告)号: US20180145015A1公开(公告)日: 2018-05-24
- 发明人: Kuo-Ting Lin , Chia-Wei Chang
- 申请人: Powertech Technology Inc.
- 申请人地址: TW Hsinchu County
- 专利权人: Powertech Technology Inc.
- 当前专利权人: Powertech Technology Inc.
- 当前专利权人地址: TW Hsinchu County
- 优先权: TW104143306 20151223
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L21/56 ; H01L23/538 ; H01L23/00 ; H01L25/065 ; H01L21/48
摘要:
A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.
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