公开(公告)号：US09673178B2

公开(公告)日：2017-06-06

申请号：US14970558

申请日：2015-12-16

申请人： Powertech Technology Inc.

发明人： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20170110439A1

公开(公告)日：2017-04-20

申请号：US14970558

申请日：2015-12-16

申请人： Powertech Technology Inc.

发明人： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20180145015A1

公开(公告)日：2018-05-24

申请号：US15876210

申请日：2018-01-22

申请人： Powertech Technology Inc.

发明人： Kuo-Ting Lin ,  Chia-Wei Chang

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/1816 ,  H01L2924/18162

摘要： A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.

公开(公告)号：US10121736B2

公开(公告)日：2018-11-06

申请号：US15876210

申请日：2018-01-22

申请人： Powertech Technology Inc.

发明人： Kuo-Ting Lin ,  Chia-Wei Chang

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

摘要： A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.

公开(公告)号：US09899307B2

公开(公告)日：2018-02-20

申请号：US15245605

申请日：2016-08-24

申请人： POWERTECH TECHNOLOGY INC.

发明人： Kuo-Ting Lin ,  Chia-Wei Chang

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/1816 ,  H01L2924/18162

摘要： A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.

公开(公告)号：US09837384B2

公开(公告)日：2017-12-05

申请号：US15245653

申请日：2016-08-24

申请人： POWERTECH TECHNOLOGY INC.

发明人： Chia-Wei Chang ,  Kuo-Ting Lin

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78 ,  H01L23/04 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0239 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06179 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. A bottom surface of the encapsulant is formed when forming the encapsulant. The first redistribution layer has a plurality of connecting surfaces exposed on the bottom surface of the encapsulant. The dielectric layer is formed on the bottom surface of the encapsulant without covering the connecting surfaces. The second redistribution layer includes a plurality of bump pads coupled to the connecting surfaces. The fan-out circuitry is covered by the dielectric layer. Thereby, a multi-chip package is able to reduce possible damages to the active surfaces and bonding pads of the chips during packaging process.

公开(公告)号：US09761568B2

公开(公告)日：2017-09-12

申请号：US15383560

申请日：2016-12-19

申请人： POWERTECH TECHNOLOGY INC.

发明人： Li-Chih Fang ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/11 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/304

CPC分类号： H01L25/117 ,  H01L21/304 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/69 ,  H01L24/70 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/18162 ,  H01L2224/83005

摘要： A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.

公开(公告)号：US09716080B1

公开(公告)日：2017-07-25

申请号：US15361073

申请日：2016-11-25

申请人： Powertech Technology Inc.

发明人： Yong-Cheng Chuang ,  Chia-Wei Chang

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/43 ,  H01L24/46 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73217 ,  H01L2224/83005 ,  H01L2224/92144 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires.

公开(公告)号：US10128211B2

公开(公告)日：2018-11-13

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/16 ,  H01L21/56

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

公开(公告)号：US20180211936A1

公开(公告)日：2018-07-26

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.