Invention Application
- Patent Title: STACKED INSTRUMENT ARCHITECTURE FOR TESTING AND VALIDATION OF ELECTRONIC CIRCUITS
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Application No.: US15393640Application Date: 2016-12-29
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Publication No.: US20180188288A1Publication Date: 2018-07-05
- Inventor: Erkan Acar , Abram M. Detofsky , Jin Pan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R1/04
- IPC: G01R1/04 ; G01R31/28

Abstract:
In one embodiment, a device to test one or more electronic components comprises a first card comprising a first test device communicatively coupled to at least a first connector assembly positioned on the first card and a second card comprising a second test device communicatively coupled to at least a second connector assembly positioned on the second card. The at least a first connector assembly is directly communicatively coupled to the at least a second connector assembly to provide a direct communication interface between the first test device and the second test device that is not routed via a backplane. Other embodiments may be described.
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