- 专利标题: ADVANCED NODE COST REDUCTION BY ESD INTERPOSER
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申请号: US15743996申请日: 2015-09-14
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公开(公告)号: US20180204831A1公开(公告)日: 2018-07-19
- 发明人: Georg SEIDEMANN , Christian GEISSLER , Klaus REINGRUBER
- 申请人: Intel IP Corporation
- 国际申请: PCT/US2015/049923 WO 20150914
- 主分类号: H01L27/02
- IPC分类号: H01L27/02 ; H01L23/00 ; H01L23/48 ; H01L25/065 ; H01L25/18
摘要:
An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
公开/授权文献
- US10446541B2 Advanced node cost reduction by ESD interposer 公开/授权日:2019-10-15