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    PACKAGE DEVICES HAVING A BALL GRID ARRAY WITH SIDE WALL CONTACT PADS
    1.
    发明申请
    PACKAGE DEVICES HAVING A BALL GRID ARRAY WITH SIDE WALL CONTACT PADS 审中-公开

    公开(公告)号：US20200066692A1

    公开(公告)日：2020-02-27

    申请号：US16344633

    申请日：2016-12-14

    申请人： INTEL IP CORPORATION

    发明人： Andreas WOLTER ,  Bernd WAIDHAS ,  Georg SEIDEMANN ,  Klaus REINGRUBER ,  Thomas WAGNER

    IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

    摘要： Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.

    SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE
    6.
    发明申请
    SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE 审中-公开

    公开(公告)号：US20200176436A1

    公开(公告)日：2020-06-04

    申请号：US15776378

    申请日：2015-12-23

    申请人： Intel IP Corporation

    发明人： Sven ALBERS ,  Klaus REINGRUBER ,  Richard PATTEN ,  Georg SEIDEMANN ,  Christian GEISSLER

    IPC分类号： H01L25/00 ,  H01L25/065

    摘要： An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

    PACKAGES OF STACKING INTEGRATED CIRCUITS
    7.
    发明申请
    PACKAGES OF STACKING INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190393191A1

    公开(公告)日：2019-12-26

    申请号：US16464213

    申请日：2016-12-27

    申请人： Intel IP Corporation

    发明人： Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Bernd WAIDHAS ,  Thomas WAGNER

    IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

    摘要： Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.