公开(公告)号：US20200066692A1

公开(公告)日：2020-02-27

申请号：US16344633

申请日：2016-12-14

申请人： INTEL IP CORPORATION

发明人： Andreas WOLTER ,  Bernd WAIDHAS ,  Georg SEIDEMANN ,  Klaus REINGRUBER ,  Thomas WAGNER

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

摘要： Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.

公开(公告)号：US20190043800A1

公开(公告)日：2019-02-07

申请号：US16152221

申请日：2018-10-04

申请人： Intel IP Corporation

发明人： Klaus Jürgen REINGRUBER ,  Sven ALBERS ,  Christian Georg GEISSLER ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Marc DITTES

IPC分类号： H01L23/528 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  C25D5/10 ,  C25D7/12 ,  C25D5/02 ,  H01L23/522 ,  C25D5/48 ,  C25D5/54 ,  H05K1/02

摘要： Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20180358317A1

公开(公告)日：2018-12-13

申请号：US15776051

申请日：2015-12-23

申请人： Intel IP Corporation

发明人： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/552 ,  H01L23/433 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

摘要： An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20180226377A1

公开(公告)日：2018-08-09

申请号：US15748115

申请日：2015-08-27

申请人： INTEL IP CORPORATION

发明人： Christian GEISSLER ,  Georg SEIDEMANN

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/02 ,  H05K1/11

CPC分类号： H01L25/065 ,  H01L21/02362 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/24137 ,  H01L2224/27849 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2924/01029 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K1/111 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/014

摘要： Embodiments may relate to an embedded package having a diffusion barrier layer may be placed between a copper (Cu) pad and a solder ball inside the embedded package. During the solder reflow process, an intermetallic compound (IMC) layer is created that does not come into contact with the Cu, so that subsequent high temperatures applied to the embedded package may not cause the Cu to be consumed through diffusion. Other embodiments may be described and/or claimed.

公开(公告)号：US20200328182A1

公开(公告)日：2020-10-15

申请号：US16915282

申请日：2020-06-29

申请人： Intel IP Corporation

发明人： Bernd WAIDHAS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Thomas WAGNER ,  Stephan Stoeckl ,  Laurent MILLOU

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

摘要： An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20180331053A1

公开(公告)日：2018-11-15

申请号：US15776474

申请日：2015-12-21

申请人： Intel IP Corporation

发明人： Christian GEISSLER ,  Sven ALBERS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thomas WAGNER ,  Marc DITTES

IPC分类号： H01L23/00

摘要： An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20180204831A1

公开(公告)日：2018-07-19

申请号：US15743996

申请日：2015-09-14

申请人： Intel IP Corporation

发明人： Georg SEIDEMANN ,  Christian GEISSLER ,  Klaus REINGRUBER

IPC分类号： H01L27/02 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L27/0296 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L27/0255 ,  H01L28/00 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48157 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2224/45099

摘要： An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

公开(公告)号：US20180218962A1

公开(公告)日：2018-08-02

申请号：US15748475

申请日：2015-08-31

申请人： INTEL IP CORPORATION

发明人： Christian GEISSLER ,  Georg SEIDEMANN ,  Sonja KOLLER ,  Jan PROSCHWITZ

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/563 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/073 ,  H01L25/074 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32141 ,  H01L2224/32507 ,  H01L2224/33519 ,  H01L2924/15153

摘要： Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.

公开(公告)号：US20200273832A1

公开(公告)日：2020-08-27

申请号：US16871325

申请日：2020-05-11

申请人： Intel IP Corporation

发明人： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC分类号： H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L23/552 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

摘要： An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200176436A1

公开(公告)日：2020-06-04

申请号：US15776378

申请日：2015-12-23

申请人： Intel IP Corporation

发明人： Sven ALBERS ,  Klaus REINGRUBER ,  Richard PATTEN ,  Georg SEIDEMANN ,  Christian GEISSLER

IPC分类号： H01L25/00 ,  H01L25/065

摘要： An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.