Invention Application
- Patent Title: BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS
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Application No.: US15723308Application Date: 2017-10-03
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Publication No.: US20180210993A1Publication Date: 2018-07-26
- Inventor: Yen-Hung LIN , Yuan-Te HOU , Chung-Hsing WANG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.
Public/Granted literature
- US10515175B2 Block-level design method for heterogeneous PG-structure cells Public/Granted day:2019-12-24
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