公开(公告)号：US20210264092A1

公开(公告)日：2021-08-26

申请号：US17314988

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39

Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

公开(公告)号：US20150095857A1

公开(公告)日：2015-04-02

申请号：US14043890

申请日：2013-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung HSU ,  Chin-Chang HSU ,  Yuan-Te HOU ,  Godina HO ,  Wen-Hao CHEN ,  Wen-Ju YANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70466 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

Abstract translation: 集成电路的单层布局的一部分是多图案化的。 用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。 每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。 该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。

公开(公告)号：US20140059504A1

公开(公告)日：2014-02-27

申请号：US14068006

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

公开(公告)号：US20210390240A1

公开(公告)日：2021-12-16

申请号：US17404511

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung CHANG ,  Yuan-Te HOU ,  Chung-Hsing WANG ,  Yung-Chin HOU

IPC: G06F30/392 ,  G06F30/20 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394 ,  G06F30/327

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

公开(公告)号：US20170133321A9

公开(公告)日：2017-05-11

申请号：US13859797

申请日：2013-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

公开(公告)号：US20240086610A1

公开(公告)日：2024-03-14

申请号：US18513349

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F30/392 ,  G06F30/39

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/398

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US20230306181A1

公开(公告)日：2023-09-28

申请号：US18327557

申请日：2023-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39

CPC classification number: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39 ,  G06F2119/10

Abstract: A method performed by a computer system includes: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device; determining leakage probabilities according to the cell abutment cases; calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values; and generating a layout of the semiconductor device according to the expected boundary leakages. Two of the leakage probabilities correspond to two of the cell abutment cases, respectively, and the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other.

公开(公告)号：US20180165406A1

公开(公告)日：2018-06-14

申请号：US15595863

申请日：2017-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung LIN ,  Yuan-Te HOU ,  Chin-Chang HSU

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F2217/12

Abstract: A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.

公开(公告)号：US20230205966A1

公开(公告)日：2023-06-29

申请号：US18173731

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung CHANG ,  Yuan-Te HOU ,  Chung-Hsing WANG ,  Yung-Chin HOU

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/0886 ,  G06F30/394

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

公开(公告)号：US20200226229A1

公开(公告)日：2020-07-16

申请号：US16586658

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua LIU ,  Yun-Xiang LIN ,  Yuan-Te HOU ,  Chung-Hsing WANG

IPC: G06F17/50

Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.